Monolithic 3D layout using 2D EDA for embedded memory-rich designs

Abstract

Monolithic 3D integration has generated considerable interest in recent years due it its inherent capability of supporting heterogeneous devices, and its rich vertical connectivity allowing for increased integration while reducing wire-length and power. Few commercial EDA 3D tools are in existence and prior work focused on partitioning logic between two or more logic strata, capitalizing on harnessing existing 2D tools into 3D flows through scripting and other strategies. In this paper we present a methodology intended to exploit the memory-rich nature of modern designs that have large fractions of their area dedicated to multiple memory blocks, and leverages 3D stacking to partition the design into memory-optimized and logic-optimized strata using commercial Synopsys 2D EDA tools.