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A method of hardware implementation of membrane computing architectures for mobile robot control

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dc.contributor.author ABABII, Victor
dc.contributor.author SUDACEVSCHI, Viorica
dc.contributor.author CARBUNE, Viorel
dc.contributor.author MUNTEANU, Silvia
dc.contributor.author ALEXEI, Victoria
dc.contributor.author LASCO, Victor
dc.date.accessioned 2025-02-24T12:05:22Z
dc.date.available 2025-02-24T12:05:22Z
dc.date.issued 2022
dc.identifier.citation ABABII, Victor; Viorica SUDACEVSCHI; Viorel CARBUNE; Silvia MUNTEANU; Victoria ALEXEI and Victor LASCO. A method of hardware implementation of membrane computing architectures for mobile robot control. In: 16th International Conference on Development and Application Systems, DAS, Romania, Suceava, 26-28 May, 2022. Institute of Electrical and Electronics Engineers, 2022, pp. 52-56. ISBN 978-16-65481-63-2, eISBN 978-16-65481-62-5. en_US
dc.identifier.isbn 978-16-65481-63-2
dc.identifier.isbn 978-16-65481-62-5
dc.identifier.uri https://doi.org/10.1109/DAS54948.2022.9786079
dc.identifier.uri https://repository.utm.md/handle/5014/29883
dc.description Access full text: https://doi.org/10.1109/DAS54948.2022.9786079 en_US
dc.description.abstract This paper proposes a method of hardware implementation of the membrane computing architecture for the control of a mobile robot. The basic idea is to use in the development of control systems the models of functional description of living cells, which should ensure a process of design, modeling and implementation based on cognitive models. The implementation algorithm presents a sequence of operations involving: functional development and modeling of Computing Cells, development and modeling of the topology of the membrane computing system (P-System), their implementation in hardware description languages (AHDL), and configuration of the FPGA circuit for realization of the control system. For validation and analysis of the performance of the Computing Cells, Petri Net models are used, which ensure the identification of the concurrent processes while maintaining a maximum parallelism. Functional testing of membrane computing models was performed based on the Quartus II development environment, the AHDL hardware description language, and the Altera DE0 Board. en_US
dc.language.iso en en_US
dc.publisher Institute of Electrical and Electronics Engineers en_US
dc.rights Attribution-NonCommercial-NoDerivs 3.0 United States *
dc.rights.uri http://creativecommons.org/licenses/by-nc-nd/3.0/us/ *
dc.subject membrane computing en_US
dc.subject mobile robot control en_US
dc.subject hardware implementation en_US
dc.title A method of hardware implementation of membrane computing architectures for mobile robot control en_US
dc.type Article en_US


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