Design and partitioning across 2 strata in 3D IC architectures

Abstract

The 2D tools used for producing integrated circuits can be adapted for de 3D integration taking into consideration the design, technological files and methodology used for implementation. A suitable design for 3D integration using 2D instruments should have about half memory area and half standard cells area, memories going to the 2nd stratum and standard cells remaining on the 1st stratum. Usually these 2 strata will have different placement utilization, but anyhow much smaller than 100% (this is very depended by design size and shape as well as by memories’ size, shape and number).