Constrained-Random Verification for Synthesis: Tools and Results

Abstract

This paper presents the tools for automation the synthesis of constrained-random generator for verification the synthesizable designs of microprocessors and microcontrollers. The structure of constrained-random generator is coded by a stochastic grammar that is defined using the elaborated tools. Various constrained-random parameters, inclusively simulation coverage, can be estimated thanks to correspondence between stochastic grammar and the Markov chain. The performed test experiments have showed that the apriori estimations and aposteriori test results are in good agreement.