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FPGA - based implementation of safe Petri nets models

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dc.contributor.author ABABII, V.
dc.contributor.author SUDACEVSCHI, V.
dc.date.accessioned 2019-11-13T07:53:56Z
dc.date.available 2019-11-13T07:53:56Z
dc.date.issued 2005
dc.identifier.citation ABABII, V., SUDACEVSCHI, V. FPGA - based implementation of safe Petri nets models. In: Microelectronics and Computer Science: proc. of the 4th intern. conf., September 15-17, 2005. Chişinău, 2005, vol. 2, pp. 226-229. ISBN 9975-66-038-X. en_US
dc.identifier.isbn 9975-66-038-X
dc.identifier.uri http://repository.utm.md/handle/5014/6738
dc.description.abstract In this paper a hardware implementation method of Safe Petri Nets (SaPN) models is proposed. Mapping of SaPN models into FPGA is based on creating of the connections between selected functional elements places P and transitions T according to the incidence matrix. The method allows the implementation of SaPN models of any complexity by reason of flexible architecture of functional elements. Proposed method makes possible the economical and structured FPGA implementation according to AHDL description of processing elements. en_US
dc.language.iso en en_US
dc.publisher Technical University of Moldova en_US
dc.rights Attribution-NonCommercial-NoDerivs 3.0 United States *
dc.rights.uri http://creativecommons.org/licenses/by-nc-nd/3.0/us/ *
dc.subject Petri nets en_US
dc.subject FPGA en_US
dc.subject data processing en_US
dc.title FPGA - based implementation of safe Petri nets models en_US
dc.type Article en_US


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