A Hardware Implementation of Petri Nets Models

SUDACEVSCHI, Viorica; GUTULEAC, Ludmila; ABABII, Victor

dc.contributor.author	SUDACEVSCHI, Viorica
dc.contributor.author	GUTULEAC, Ludmila
dc.contributor.author	ABABII, Victor
dc.date.accessioned	2021-09-01T10:24:53Z
dc.date.available	2021-09-01T10:24:53Z
dc.date.issued	2004
dc.identifier.citation	SUDACEVSCHI, Viorica, GUTULEAC, Ludmila, ABABII, Victor. A Hardware Implementation of Petri Nets Models. In: Development and application systems: proc. of 7th International Conference. 27 – 29 May 2004, Suceava, Romania. 2004, pp. 24-28.	en_US
dc.identifier.uri	http://repository.utm.md/handle/5014/16852
dc.description.abstract	This paper presents the structure of a reconfigurable FPGA system for Petri Net simulation. The system is described as the interactions between processed elements that are functionally defined. According to the interconnection mode of the processed elements Petri Net models with any complexity can be implemented. The processed elements have a flexible architecture that allows their adaptation to the simulation of Petri Net model. The processed elements architecture and their interconnection mode gives the possibility to reduce the execution time that is necessary for reachability analysis of Petri Net.	en_US
dc.language.iso	en	en_US
dc.publisher	Stefan cel Mare University of Suceava, Romania	en_US
dc.rights	Attribution-NonCommercial-NoDerivs 3.0 United States	*
dc.rights.uri	http://creativecommons.org/licenses/by-nc-nd/3.0/us/	*
dc.subject	Petri nets	en_US
dc.title	A Hardware Implementation of Petri Nets Models	en_US
dc.type	Article	en_US