HDL Implementation from Petri Nets Description

Abstract

This paper describes the digital systems synthesis based on direct mapping of Petri nets model into FPGA circuit. A design flow that includes the specification of the system using Synchronous Petri Nets, verification of the behavioral properties of the model, generation of the mathematical model of Hard Petri Nets (HPN), used for automatic generation of the AHDL code is described. The direct mapping approach avoids algorithmic complexity inherent in logic synthesis based on state encoding and substantially reduces the design time and cost. The method used for modelling and implementation of the digital systems was validated using MAX+PLUS II design environment.